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 STL15N3LLH5
N-channel 30 V, 0.0045 15 A, PowerFLATTM (3.3 x 3.3) , STripFETTM V Power MOSFET
Preliminary Data
Features
Type STL15N3LLH5 VDSS 30V RDS(on) <0.0054 ID 15A (1)
1. The value is rated according Rthj-pcb
RDS(on) * Qg industry benchmark Extremely low on-resistance RDS(on) Very low switching gate charge High avalanche ruggedness Low gate drive power losses
PowerFLATTM(3.3x3.3) (Chip scale package)
Applications
Switching applications
Figure 1.
Internal schematic diagram
Description
This product utilizes the 5th generation of design rules of ST's proprietary STripFETTM technology. The lowest available RDS(on)*Qg, in this chip scale package, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved.
Table 1.
Device summary
Order code Marking 15N3LLH5 Package PowerFLATTM (3.3 x 3.3) Packaging Tape and reel
STL15N3LLH5
August 2008
Rev 1
1/10
www.st.com 10
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STL15N3LLH5
Contents
1 2 3 4 5 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Test circuit ................................................ 6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
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STL15N3LLH5
Electrical ratings
1
Electrical ratings
Table 2.
Symbol VDS VGS ID(1) ID (1) IDM
(2)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Total dissipation at TC = 25 C Total dissipation at TC = 25 C Derating factor Value 30 22 15 9.3 60 50 2 0.4 -55 to 150 Unit V V A A A W W W/C C
PTOT(3) PTOT(1)
TJ Tstg
Operating junction temperature storage temperature
1. The value is rated according Rthj-pcb 2. Pulse width limited by safe operating area. 3. The vaule is rated according Rthj-c
Table 3.
Symbol Rthj-case Rthj-pcb Rthj-pcb
(1) (2)
Thermal resistance
Parameter Thermal resistance junction-case (drain) Thermal resistance junction-pcb Thermal resistance junction-pcb Value 2.5 42.8 63.5 Unit C/W C/W C/W
1. When mounted on FR-4 board of 1inch, 2oz Cu, t < 10sec 2. Steady state
3/10
Electrical characteristics
STL15N3LLH5
2
Electrical characteristics
(TCASE=25C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating @125 C VGS = 22 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 7.5 A VGS= 4.5 V, ID= 7.5 A 1 Min. 30 1 10
100
Typ.
Max.
Unit V A A nA V
2.5 0.0045 0.0054 0.006 0.0075
Table 5.
Symbol Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS =25 V, f=1 MHz, VGS=0 VDD=15 V, ID = 15 A VGS =4.5 V (see Figure 3) f=1 MHz Gate DC Bias = 0 Test signal level = 20 mV Open drain 0.5 Min. Typ. 1500 295 39 12 4 4.7 Max. Unit pF pF pF nC nC nC
Gate input resistance
1.5
2.5
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STL15N3LLH5
Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=15 V, ID= 7.5 A, RG=4.7 , VGS=4.5 V (see Figure 2) Min. Typ. 9.3 14.5 22.7 4.5 Max. Unit ns ns ns ns
Table 7.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD=15 A, VGS=0 ISD=15 A, di/dt = 100 A/s, VDD=20 V, Tj=150 C (see Figure 7) 25 17.5 1.4 Test conditions Min. Typ. Max. 15 60 1.1 Unit A A V ns nC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300s, duty cycle 1.5%
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Test circuit
STL15N3LLH5
3
Figure 2.
Test circuit
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
Figure 4.
Test circuit for inductive load Figure 5. switching and diode recovery times
Unclamped inductive load test circuit
Figure 6.
Unclamped inductive waveform
Figure 7.
Switching time waveform
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STL15N3LLH5
Package mechanical data
4
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
7/10
Package mechanical data
STL15N3LLH5
PowerFLATTM ( 3.3 x 3.3) mechanical data
mm Dim Min A A3 b D D2 E E2 e L L1 0.45 0.29 3.200 2.24 2.20 1.660 0.950 0.200 0.34 3.300 2.29 3.30 1.710 0.650 0.40 0.50 0.55 0.017 0.39 3.400 2.34 3.40 1.760 0.011 0.126 0.088 0.086 0.065 Typ Max 1.000 Min 0.037
inch Typ Max 0.039 0.008 0.013 0.123 0.090 0.123 0.067 0.025 0.0157 0.0196 0.021 0.015 0.134 0.092 0.1338 0.069
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STL15N3LLH5
Revision history
5
Revision history
Table 8.
Date 25-Aug-2008
Document revision history
Revision 1 First release Changes
9/10
STL15N3LLH5
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